The development of SK Hynix’s server-tier MCR DIMMs, which offer memory modules rated at DDR5-8000 and beyond, was recently revealed by the company.

SK Hynix Is Beginning Development On MCR DIMM, Which Will Include A Minimum Of 8 Gbps DDR5 Modules For Servers

SK Hynix has revealed today that it has created functional samples of the DDR5 Multiplexer Combined Ranks (MCR) Dual In-line Memory Module, the world’s fastest server DRAM product. This announcement was made in the form of a press release.

It has been established that the new product would function at a data rate of no less than 8 Gbps, which is at least 80% higher than the 4.8 Gbps attained by the present DDR5 products.

Up to the fifth generation, the DRAM standard known as Double Data Rate (DDR) has been created. This standard is mainly utilized for client and server applications. The MCR DIMM is a module product that offers better speed as a consequence of two ranks running concurrently. This is made possible by the multiple DRAM chips that are coupled to the board of the module.

A collection of the data’s fundamental transfer units transmitted to the CPU from the DRAM module. Also known as “rank.” A rank is commonly understood to refer to a bundle of data consisting of 64 bytes that must be sent to the central processor unit.

MCR DIMM is an accomplishment that resulted from thinking outside the box to enhance the performance of DDR5 memory modules. To create the most recent version of the product, the engineers wanted to find a way to improve the speed of the modules rather than the chips themselves. This was done to challenge the widely held belief that the rate of operation of DDR5 is dependent on the speed of the DRAM chip itself.

By making use of the data buffer that is loaded onto the MCR DIMM, which is based on the MCR technology developed by Intel, SK Hynix was able to construct the product in such a manner that it permits the simultaneous functioning of two ranks.

A component known as a buffer is an element that improves the efficiency of signal transfer between DRAM and CPU—installed mostly into modules for servers that require high levels of both performance and durability.

The transfer of 128 bytes of data to the CPU is made possible by MCR DIMM because it enables the simultaneous functioning of two ranks. This is in contrast to the standard number of 64 bytes that are fetched by standard DRAM modules. A data transmission rate of at least 8 Gbps may be supported by a rise in the quantity of data that is transmitted to the CPU at each time. This is twice as fast as a single DRAM.

The key to our company’s success was working closely with our business partners at Intel and Renesas. The three businesses collaborated and helped each other throughout the process, from the initial product design to the final verification.

According to Sungsoo Ryu, Head of DRAM Product Planning at SK Hynix, the accomplishment was made possible due to the convergence of several diverse technologies.

“SK hynix’s DRAM module-designing capabilities were met with Intel’s excellence in Xeon processor and Renesas’ buffer technology,” 

Ryu stated.

“For a stable performance of MCR DIMM, smooth interactions between the data buffer and processor in and out of the module are essential.”

The data buffer is responsible for transmitting various signals that originate from the module in the center, and the server CPU is responsible for accepting and processing signals that arrive via the buffer.

“SK hynix delivered another technological evolution for DDR5 by developing the world’s fastest MCR DIMM,” Ryu said. “Our efforts to find technological breakthroughs will continue as we seek to solidify our leadership in the server DRAM market.”

According to Dr. Dimitrios Ziakas, Vice President of Memory and IO Technologies at Intel, Intel and SK Hynix are leading the way in memory innovation and the development of high-performance, scalable DDR5 for servers, together with other major industry partners. Dr. Ziakas made this statement.

“The technology brought forward comes from years of collaborative research between Intel and key industry partners to produce significant increases in deliverable bandwidth for Intel Xeon processors,” he said. “We look forward to bringing this technology to future Intel Xeon processors and supporting standardization and multigenerational development efforts across the industry.”

Sameer Kuppahalli, Vice President and General Manager of the Memory Interface Division at Renesas, stated that the development of the data buffer by Renesas is the culmination of three years of intensive effort spanning from concept to productization. Kuppahalli noted that the development of the data buffer took place over three years.

“We’re proud to partner with SK Hynix and Intel in the endeavor to realize this technology into a compelling product,” 

He stated.

SK Hynix anticipates that high-performance computing will drive growth in the market for MCR DIMMs since this type of computing will benefit from enhanced memory bandwidth. In the not-too-distant future, SK Hynix intends to begin producing the product on a large scale.

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