RISC-V company Ventana Microsystems has just begun the process of designing and releasing its first worldwide server-based processor, which is called the Veyron V1. This endeavor makes use of cutting-edge 5nm manufacturing technology.
Introducing this brand-new server CPU would place the young company in direct rivalry with AMD and Intel, which provide the EPYC and Xeon server processors. This information was presented at the RISC-V Summit that took place today in San Jose, California.
RISC-V architecture is widely used in the Internet of Things marketplace due to its ability to provide efficient energy use, open-source capability, cutting-edge instructions, and scalability of its hardware. Ventana Microsystems, a startup company, aims to take on AMD and Intel in the ring of server-side processors with its RISC-V chips, the Veyron V1. RISC-V architecture is the predominant architecture used in the IoT marketplace.
It would make perfect sense to expand its technological capabilities on a broader scale, including establishing servers and data centers, which are rapidly becoming indispensable components of modern civilization.
The new V1 chip from Veyron features a RISC-V core fabricated using the 5nm manufacturing technology. The device has an architecture with eight pipelines, clock speeds of up to 3.6 GHz, and a total of 192 cores, which are distributed over 16 clusters.
In addition, the Veyron V1 chip possesses advanced security features such as sid-channel attack mitigations, IOMMU and AIA technologies, thorough RAS functionalities, and performance tuning through top-down software methodology. The L3 cache on the Veyron V1 chip has a capacity of 48 megabytes, and it can also support “out-of-order execution.”
The capability of Veyron to have this chip utilized in an increased number of products and services is the aspect of delivering this chip to a broader market is the most critical factor. As can be seen, Veyron intends to put the V1 chip to use in a variety of various server applications, including storage, web hosting, data centers, and streaming services.
The data connections are located along one side of the chip, memory is on either side, and the PCIe Gen5 connector is located in the center of the chip. The general architecture of the chip has a similar layout structure as the new EPYC CPUs from AMD (with backward compatibility with Gen4).
The Die-to-Die (D2D) interface is compatible with the Harness of Wire (HoW) and the Universal Chiplet Interconnect Express (UCIe), both of which are supported by more giant corporations such as AMD, Intel, NVIDIA, and Arm, in addition to a significant number of other businesses.
Drew Henry, Executive VP of Strategy and Marketing at Arm, is pleased to see greater competition in the ecosystem and new faces like Ventana Microsystems. He welcomes both of these developments.
He points out that with the growing need for hardware for HPC, cloud, AI, and other applications, having more firms participate will benefit the market rather than hurt it. This would allow technology to advance without being hampered by a supply shortage, enabling it to thrive. Executives at Arm have been quoted as saying, “We appreciate RISC-V, but it is not yet a competitor.”
The new Veyron V1 is being actively marketed to more businesses to increase their sales and decrease their overall production expenses so that they can make more chips. The company’s goal is to reduce the time required for development by two years, resulting in cost savings of up to $75 million in research and development alone.